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Am29F032B
Data Sheet
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Publication Number 21610 Revision D
Amendment +1 Issue Date December 5, 2000
Am29F032B
32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V 10%, single power supply operation -- Minimizes system level power requirements s Manufactured on 0.32 m process technology s High performance -- Access times as fast as 70 ns s Low power consumption -- 30 mA typical active read current -- 30 mA typical program/erase current -- <1 A typical standby current (standard access time to active mode) s Flexible sector architecture -- 64 uniform sectors of 64 Kbytes each -- Any combination of sectors can be erased. -- Supports full chip erase -- Group sector protection: -- A hardware method of locking sector groups to prevent any program or erase operations within that sector group -- Temporary Sector Group Unprotect allows code changes in previously locked sectors s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies bytes at specified addresses s Minimum 1,000,000 write/erase cycles guaranteed s 20-year data retention at 125C -- Reliable operation for the life of the system s Package options -- 40-pin TSOP -- 44-pin SO s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply Flash standard -- Superior inadvertent write protection s Data# Polling and toggle bits -- Provides a software method of detecting program or erase cycle completion s Ready/Busy output (RY/BY#) -- Provides a hardware method for detecting program or erase cycle completion s Erase Suspend/Resume -- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation s Hardware reset pin (RESET#) -- Resets internal state machine to the read mode
This Data Sheet states AMD's current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21610 Rev: D Amendment/+1 Issue Date: December 5, 2000
GENERAL DESCRIPTION
The Am29F032B is a 32 Mbit, 5.0 volt-only Flash memory organized as 4,194,304 bytes of 8 bits each. The 4 Mbytes of data are divided into 64 sectors of 64 Kbytes each for flexible erase capability. The 8 bits of data appear on DQ0-DQ7. The Am29F032B is offered in 40-pin TSOP and 44-pin SO packages. The Am29F032B is manufactured using AMD's 0.32 m process technology. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 volt Flash or EPROM devices. The device is programmed by executing the program command sequence. This invokes the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The device is erased by executing the erase command sequence. This invokes the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within one second. The device is erased when shipped from the factory. The hardware sector group protection feature disables both program and erase operations in any combination of the eight sector groups of memory. A sector group consists of four adjacent sectors. The Erase Suspend feature enables the system to put erase on hold for any period of time to read data from, or program data to, a sector that is not being erased. True background erase can thus be achieved. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The host system can detect whether a program or erase cycle is complete by using the RY/BY# pin, the DQ7 (Data# Polling) or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to the read mode. A hardware RESET# pin terminates any operation in progress. The internal state machine is reset to the read mode. The RESET# pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during either an Embedded Program or Embedded Erase algorithm, the device is automatically reset to the read mode. This enables the system's microprocessor to read the boot-up firmware from the Flash memory. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the programming mechanism of hot electron injection.
2
Am29F032B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . Device Bus Operations . . . . . . . . . . . . . . . . . . . . . Requirements for Reading Array Data ..................................... Writing Commands/Command Sequences .............................. Program and Erase Operation Status ...................................... Standby Mode .......................................................................... RESET#: Hardware Reset Pin ................................................. Output Disable Mode................................................................ 4 4 5 6 6 7 8 8 8 9 9 9 9 DQ3: Sector Erase Timer ....................................................... 20
Figure 5. Toggle Bit Algorithm........................................................ 20 Table 6. Write Operation Status..................................................... 21
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negative Overshoot Waveform ...................... 22 Figure 7. Maximum Positive Overshoot Waveform........................ 22
Table 1. Am29F032B Device Bus Operations .................................. 8
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23 TTL/NMOS Compatible .......................................................... 23 CMOS Compatible.................................................................. 23 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup...................................................................... 24 Table 7. Test Specifications ........................................................... 24
Table 2. Am29F032B Sector Address Table................................... 10
Autoselect Mode..................................................................... 11
Table 3. Am29F032B Autoselect Codes ......................................... 11
Key To Switching Waveforms . . . . . . . . . . . . . . . 24 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 Read-only Operations............................................................. 25
Figure 9. Read Operation Timings ................................................. 25
Sector Group Protection/Unprotection.................................... 12
Table 4. Sector Group Addresses................................................... 12
Hardware Reset (RESET#) .................................................... 26
Figure 10. RESET# Timings .......................................................... 26
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Temporary Sector Group Unprotect Operation................ 12
Write (Erase/Program) Operations ......................................... 27
Figure 11. Program Operation Timings.......................................... Figure 12. Chip/Sector Erase Operation Timings .......................... Figure 13. Data# Polling Timings (During Embedded Algorithms). Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... Figure 15. DQ2 vs. DQ6................................................................. 28 29 30 30 31
Hardware Data Protection ...................................................... 13
Low VCC Write Inhibit..................................................................... 13 Write Pulse "Glitch" Protection ........................................................ 13 Logical Inhibit .................................................................................. 13 Power-Up Write Inhibit .................................................................... 13
Temporary Sector Unprotect .................................................. 31
Figure 16. Temporary Sector Group Unprotect Timings ................ 31
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13 Reading Array Data ................................................................ 13 Reset Command..................................................................... 13 Autoselect Command Sequence ............................................ 14 Byte Program Command Sequence....................................... 14 Chip Erase Command Sequence ........................................... 14
Figure 2. Program Operation .......................................................... 15
Write (Erase/Program) Operations--Alternate CE# Controlled Writes .................................................................... 32
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 33
Sector Erase Command Sequence ........................................ 15 Erase Suspend/Erase Resume Commands........................... 15
Figure 3. Erase Operation............................................................... 16
Command Definitions ............................................................. 17
Table 5. Am29F032B Command Definitions................................... 17
Write Operation Status . . . . . . . . . . . . . . . . . . . . 18 DQ7: Data# Polling................................................................. 18
Figure 4. Data# Polling Algorithm ................................................... 18
RY/BY#: Ready/Busy# ........................................................... DQ6: Toggle Bit I .................................................................... DQ2: Toggle Bit II ................................................................... Reading Toggle Bits DQ6/DQ2 .............................................. DQ5: Exceeded Timing Limits ................................................
19 19 19 19 20
Erase And Programming Performance . . . . . . . 34 Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 34 TSOP And SO Pin Capacitance . . . . . . . . . . . . . 34 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 35 SO 044-44-Pin Small Outline Package.................................. 35 TS 040-40-Pin Standard Thin Small Outline Package........... 36 TSR040-40-Pin Reversed Thin Small Outline Package ........ 37 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision A (June 1998) .......................................................... 38 Revision B (July 1998)............................................................ 38 Revision C (January 1999) ..................................................... 38 Revision C+1 (April 14, 1999)................................................. 38 Revision D (November 17, 1999) ........................................... 38 Revision D+1 (December 5, 2000) ......................................... 38
Am29F032B
3
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) VCC = 5.0 V 5% VCC = 5.0 V 10% 70 70 40 -75 -90 90 90 40 -120 120 120 50 -150 150 150 75 Am29F032B
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
DQ0-DQ7 VCC VSS RY/BY# RESET# State Control Command Register Sector Switches Erase Voltage Generator Input/Output Buffers
WE#
PGM Voltage Generator Chip Enable Output Enable STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A21
4
Am29F032B
CONNECTION DIAGRAMS
A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A20 A21 WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
40-Pin Standard TSOP
A20 A21 WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40-Pin Reverse TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC NC RESET# A11 A10 A9 A8 A7 A6 A5 A4
NC RESET# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC A20 A21 WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC
Am29F032B
5
PIN CONFIGURATION
A0-A21 CE# WE# OE# RESET# RY/BY# VCC = = = = = = 22 Addresses 8 Data Inputs/Outputs Chip Enable Write Enable Output Enable Hardware Reset Pin, Active Low Ready/Busy Output DQ0-DQ7 =
LOGIC SYMBOL
22 A0-A21 DQ0-DQ7 8
CE# OE# WE# RESET# RY/BY#
= +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) = = Device Ground Pin Not Connected Internally
VSS NC
6
Am29F032B
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29F032B -75 E I
TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F032B 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory 5.0 V Read, Program, and Erase
Valid Combinations AM29F032B-75 AM29F032B-90 AM29F032B-120 AM29F032B-150 EC, EI, EE, FC, FI, FE, SC, SI, SE EC, EI, FC, FI, SC, SI
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am29F032B
7
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Operation Read Write CMOS Standby TTL Standby Output Disable Hardware Reset Temporary Sector Unprotect (See Note)
Am29F032B Device Bus Operations
CE# L L OE# L H X X H X X WE# H L X X H X X RESET# H H VCC 0.5 V H H L VID A0-A21 AIN AIN X X X X AIN DQ0-DQ7 DOUT DIN High-Z High-Z High-Z High-Z DIN
VCC 0.5 V H L X X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. See the "Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data." section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing 8
Am29F032B
Characteristics" section contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "The Erase Resume command is valid only during the Erase Suspend mode." for more information, and to each AC Characteristics section for timing diagrams.
drives the RESET# pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VIL, the device enters the TTL standby mode; if RESET# is held at V SS 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at VCC 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, "RESET#: Hardware Reset Pin". If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics tables, ICC3 represents the standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
Am29F032B
9
Table 2.
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
Am29F032B Sector Address Table
A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh
10
Am29F032B
Table 2.
Sector SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Am29F032B Sector Address Table (Continued)
A18 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Size 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Address Range 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh
A19
Note: All sectors are 64 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 3. In addition, when verifying sector group proTable 3.
Description Manufacturer ID: AMD Device ID: Am29F032B Sector Group Protection Verification A21-A18 X X Sector Group Address A17-A10 X X X
tection, the sector group address must appear on the appropriate highest order address bits (see Table 4). Table 3 also shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 5. This method does not require VID on an address line. Refer to the Autoselect Command Sequence section for more information.
Am29F032B Autoselect Codes
A9 VID VID VID A8-A7 X X X A6 VIL VIL VIL A5-A2 X X X A1 VIL VIL VIH A0 VIL VIH VIL Identifier Code on DQ7-DQ0 01h 41h 01h (protected) 00h (unprotected)
Note: Identifier codes for manufacturer and device IDs exhibit odd parity with DQ7 defined as the parity bit.
Am29F032B
11
Sector Group Protection/Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. Each sector group consists of four adjacent sectors. Table 4 shows how the sectors are grouped, and the address range that each sector group contains. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID ) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 22184. Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See "Autoselect Mode" for details. Table 4.
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 A21 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID (11.5 V - 12.5 V). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 16 shows the timing diagrams, for this feature.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Sector Group Addresses
A20 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A19 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A18 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sectors SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63
Temporary Sector Group Unprotect Completed (Note 2)
Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again.
Figure 1.
Temporary Sector Group Unprotect Operation
12
Am29F032B
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO (see DC Characteristics for voltage levels), the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled. Under this condition the device resets to the read mode. Subsequent writes are ignored until the VCC level is greater
than VLKO. The system must ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be at VIL while OE# is at VIH. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next.
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13
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
hardware reset immediately terminates the programming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "The Erase Resume command is valid only during the Erase Suspend mode." for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
14
Am29F032B
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence.
No
Verify Data?
Yes No
Increment Address
Last Address?
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to "The Erase Resume command is valid only during the Erase Suspend mode." for information on these status bits. Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Yes Programming Completed
Note: See Table 5 for program command sequence.
Figure 2.
Program Operation
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s,
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter-
Am29F032B
15
minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "The Erase Resume command is valid only during the Erase Suspend mode." for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "The Erase Resume command is valid only during the Erase Suspend mode." for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information.
Figure 3.
Erase Operation
16
Am29F032B
Command Definitions
Table 5.
Cycles
Am29F032B Command Definitions
Bus Cycles (Notes 2-4)
Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID
First Addr Data RD F0 AA AA AA AA AA AA B0 30
Second Addr Data
Third Addr
Fourth Data Addr Data
Fifth Addr Data
Sixth Addr Data
1 1 4 4 4 4 6 6 1 1
RA XXX 555 555 555 555 555 555 XXX XXX
2AA 2AA 2AA 2AA 2AA 2AA
55 55 55 55 55 55
555 555 555 555 555 555
90 90 90 A0 80 80
X00 X01 SGA X02 PA 555 555
01
41
Autoselect Device ID (Note 7)
Sector Group Protect Verify (Note 8) Program Chip Erase Sector Erase Erase Suspend (Note 9) Erase Resume (Note 10)
XX00 XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30
Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21-A16 select a unique sector. SGA = Address of the sector group to be verified. Address bits A21-A18 select a unique sector group.
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits A21-A11 are don't cares for unlock and command cycles, unless SA or PA required. 5. No unlock or command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle. 8. The data is 00h for an unprotected sector group and 01h for a protected sector group.See "Autoselect Command Sequence" for more information. 9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode.
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17
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. rithms) figure in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for Data# Polling on DQ7. Figure 4 shows the Data# Polling algorithm.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys tem whether an Embedded Algor ithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is bec a us e D Q 7 m ay c ha ng e as y n c hr on ou sly w it h DQ0-DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algo-
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 4.
Data# Polling Algorithm
18
Am29F032B
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing diagrams for read, reset, program, and erase shows the relationship of RY/BY# to other signals.
The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on "DQ2: Toggle Bit II".
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the "DQ6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling"). If a program address falls within a protected sector, DQ6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and
Am29F032B
19
the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 5).
erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for DQ3.
START
Read DQ7-DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
No Read DQ7-DQ0
(Note 1)
Toggle Bit = Toggle? Yes
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector
Read DQ7-DQ0 Twice
(Notes 1, 2)
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text.
Figure 5.
Toggle Bit Algorithm
20
Am29F032B
Table 6.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 2) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 1) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
DQ7 (Note 1) DQ7# 0 1 Data DQ7#
Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information.
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21
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . -2.0 V to 7.0 V A9, OE#, RESET# (Note 2) . . . . . -2.0 V to 13.0 V All other pins (Note 1) . . . . . . . . . . -2.0 V to 7.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on output and I/O pins is VCC + 0.5 V. During voltage transitions, outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on A9, OE#, RESET# pins is -0.5V. During voltage transitions, A9, OE#, RESET# pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on A9, OE#, and RESET# is 13.0 V which may overshoot to 13.5 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses greater than those listed in this section may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns -0.5 V -2.0 V 20 ns +0.8 V 20 ns
Figure 6. Maximum Negative Overshoot Waveform
20 ns
Figure 7. Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -55C to +125C VCC Supply Voltages VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for 10% devices . . . . . . . . . .+4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
22
Am29F032B
DC CHARACTERISTICS TTL/NMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Read Current (Note 1) VCC Write Current (Notes 2, 3) VCC Standby Current (CE# Controlled) VCC Standby Current (RESET# Controlled) Input Low Level Input High Level Voltage for Autoselect and Sector VCC = 5.0 V Protect Output Low Voltage Output High Level Low VCC Lock-out Voltage IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA VCC = VCC Min 2.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.0 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIH, RESET# = VIH VCC = VCC Max, RESET# = VIL -0.5 2.0 11.5 30 40 0.4 0.4 Min Typ Max 1.0 50 1.0 40 60 1.0 1.0 0.8 VCC + 0.5 12.5 0.45 Unit A A A mA mA mA mA V V V V V V
CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 VOH2 VLKO Parameter Description Input Load Current A9 Input Load Current Output Leakage Current VCC Read Current (Note 1) VCC Write Current (Notes 2, 3) VCC Standby Current (CE# Controlled) VCC Standby Current (RESET# Controlled) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage Low VCC Lock-out Voltage VCC = 5.0 V IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min 0.85 VCC VCC - 0.4 3.2 4.2 Test Description VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.0 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VCC 0.5 V, RESET# = VCC 0.5 V RESET# = VSS 0.5 V -0.5 0.7x VCC 11.5 30 30 1 1 Min Typ Max 1.0 50 1.0 40 40 5 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA A A V V V V V V V
Notes for DC Characteristics (both tables): 1. The ICC current is typically less than 1 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase algorithm is in progress. 3. Not 100% tested.
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TEST CONDITIONS
5.0 V
Table 7.
Test Condition
Test Specifications
-75 All others 1 TTL gate 30 5 0.0-3.0 1.5 1.5 100 20 0.45-2.4 0.8 2.0 pF ns V V V Unit
Device Under Test CL 6.2 k
2.7 k
Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes are IN3064 or equivalent
Figure 8.
Test Setup
Output timing measurement reference levels
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
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Am29F032B
AC CHARACTERISTICS Read-only Operations
Parameter Symbol JEDEC tAVAV tAVQV tELQV tGLQV Std tRC tACC tCE tOE Parameter Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Min Min Max Max Min Max 20 20 20 20 0 20 Speed Options -75 70 70 70 40 -90 90 90 90 40 0 10 30 30 35 35 -120 120 120 120 50 -150 150 150 150 55 Unit ns ns ns ns ns ns ns ns ns s
tEHQZ tGHQZ tAXQX
tDF tDF tOH tReady
Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses CE# or OE# Whichever Occurs First RESET# Pin Low to Read Mode (Note 1)
Notes: 1. Not 100% tested. 2. Refer to Figure 8 and Table 7 for test specifications.
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
Figure 9.
Read Operation Timings
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25
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tREADY tREADY tRP tRH tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RY/BY# Recovery Time Test Setup Max Max Min Min Min All Speed Options 20 500 500 50 0 Unit s ns ns ns ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 10.
RESET# Timings
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Am29F032B
AC CHARACTERISTICS Write (Erase/Program) Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tBUSY Parameter Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write (OE# high to WE# low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) Max VCC Set Up Time (Note 1) WE# to RY/BY# Valid Min Min 40 40 8 50 50 60 sec s ns Min Min Min Min Min Min Min Min Min Min Typ Typ 40 45 20 7 1 40 40 45 45 0 0 0 0 50 50 -75 70 Speed Options -90 90 0 50 50 50 50 -120 120 -150 150 Unit ns ns ns ns ns ns ns ns ns ns s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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27
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tAS tWC Addresses 555h PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles)
PA
PA
tCH
A0h
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11.
Program Operation Timings
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Am29F032B
AC CHARACTERISTICS
tWC Addresses 2AAh tAS SA
555h for chip erase
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Note: SA = Sector Address. VA = Valid Address for reading status data.
Figure 12.
Chip/Sector Erase Operation Timings
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29
AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13.
Data# Polling Timings (During Embedded Algorithms)
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z
VA
VA
VA
tOE tDF
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 14.
Toggle Bit Timings (During Embedded Algorithms)
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Am29F032B
AC CHARACTERISTICS
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
Figure 15.
DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s
Note: Not 100% tested.
12 V
RESET# 0 or 5 V tVIDR Program or Erase Command Sequence CE# tVIDR 0 or 5 V
WE# tRSP RY/BY#
Figure 16.
Temporary Sector Group Unprotect Timings
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31
AC CHARACTERISTICS Write (Erase/Program) Operations--Alternate CE# Controlled Writes
Parameter Symbol JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Parameter Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Address Hold Time Read Recover Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation (Note 2) Sector Erase Operation (Note 2) Max 8 sec Min Min Min Min Min Min Min Min Min Min Typ Typ 40 45 20 7 1 40 40 45 45 0 0 0 0 50 50 -75 70 Speed Options -90 90 0 50 50 50 50 -120 120 -150 150 Unit ns ns ns ns ns ns ns ns ns ns s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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Am29F032B
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence.
Figure 17.
Alternate CE# Controlled Write Operation Timings
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33
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note 3) Typ (Note 1) 1 64 7 28.8 300 86.4 Max (Note 2) 8 Unit sec sec s sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system-level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5 V, 1,000,000 cycles (4.75 V for -75). 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 5 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTIC
Description Input Voltage with respect to VSS on I/O pins VCC Current Min -1.0 V -100 mA Max VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance VIN = 0 VOUT = 0 VIN = 0 Test Conditions Min 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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Am29F032B
PHYSICAL DIMENSIONS SO 044-44-Pin Small Outline Package
Dwg rev AC; 10/99
Am29F032B
35
PHYSICAL DIMENSIONS TS 040-40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
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Am29F032B
PHYSICAL DIMENSIONS TSR040-40-Pin Reversed Thin Small Outline Package
Dwg rev AA; 10/99
Am29F032B
37
REVISION SUMMARY Revision A (June 1998)
Initial release. Data Retention Added table.
Revision B (July 1998)
Distinctive Characteristics Changed typical active read current to 30 mA to match DC Characteristics table. Operating Ranges Corrected temperature range descriptions to "ambient."
Revision D (November 17, 1999)
AC Characteristics--Figure 11. Program Operations Timing and Figure 12. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations.
Revision C (January 1999)
Distinctive Characteristics Added 20-year data retention subbullet.
Revision D+1 (December 5, 2000)
Added table of contents. Ordering Information
Revision C+1 (April 14, 1999)
Deleted duplicate sections in the full data sheet.
Deleted burn-in option.
Trademarks
Copyright (c) 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Am29F032B

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